1. Field of the Invention
The present invention relates to a flat panel display (FPD), and more particularly to a thin film transistor (TFT) for a FPD and a manufacturing method thereof.
2. Discussion of the Related Art
Generally, the FPD includes a liquid crystal display (LCD) device, a plasma display panel (PDP) and an organic electroluminescent display device (OLED) or the like. Here, the TFT is utilized as a switching element or a driving element of the FPD.
FIG. 1 is a schematic view of a structure of an LCD according to the related art.
In FIG. 1, an LCD 3 includes upper and lower substrates 5 and 22 facing each other and a liquid crystal layer 11 between the upper and lower substrates 5 and 22.
A gate line 12 and a data line 24 crossing the gate line 12 are formed on the lower substrate 22 to define a pixel region P. A TFT T is disposed at a position adjacent to the crossing of the gate line 12 and the data line 24, and a pixel electrode 17 is connected to the TFT T and is disposed in the pixel region P. The pixel electrode 17 includes a transparent conductive material such as, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).
The TFT T includes a gate electrode 30 connected to the gate line 12, a source electrode 34 connected to the data line 24, a drain electrode 36 spaced apart from the source electrode 34, and a semiconductor layer 32 between the gate electrode 30 and the source electrode 34 and between the gate electrode 30 and the drain electrode 36.
Here, the gate line 12 provides a scanning signal from a first external circuit with the gate electrode 30 and the data line 24 provides a data signal from a second external circuit with the source electrode 34.
Further, red, green and blue sub-color filters 7a, 7b and 7c are formed on the upper substrate 5, wherein each of the red, green and blue sub-color filters 7a, 7b and 7c is repeatedly disposed in a region corresponding to the pixel region P. A black matrix 6 is formed in an intervening space between the red, green and blue sub-color filters 7a, 7b and 7c and a common electrode 9 is formed on the red, green and blue sub-color filters 7a, 7b and 7c and the black matrix 6.
Liquid crystal molecules of the liquid crystal layer 11 have an anisotropic dielectric constant and anisotropic refractive index characteristics due to their long, thin shape. In addition, two electric field generating electrodes are formed on the two substrates, respectively. Accordingly, the orientation of the liquid crystal molecules can be controlled by supplying a voltage to the two electrodes. Transmittance of the LCD panel is thus changed according to the polarization properties of the liquid crystal material.
The TFT may have various configurations. Typically, an inverted staggered type TFT of amorphous silicon or a top gate type TFT of polysilicon are utilized.
FIG. 2 is a schematic cross-sectional view of an inverted staggered type TFT according to the related art.
In FIG. 2, an inverted staggered type TFT T includes a gate electrode 52 on a substrate 50, a gate insulating layer 54 on an entire surface of the substrate 50 having the gate electrode 52, an active layer 56 on the gate insulating layer 54 over the gate electrode 52, and an ohmic contact layer 58 on the active layer 56. Here, the ohmic contact layer 58 has an opening portion 59 that exposes a central portion of the active layer 56. Source and drain electrodes 60 and 62 are formed on the ohmic contact layer 58. The source and drain electrodes 60 and 62 are spaced apart from each other by the opening portion 59. Substantially, the opening portion 59 defines a channel portion (not shown) of the TFT T.
Further, a passivation layer 64 is formed on the TFT T. The passivation layer 64 has a drain contact hole 66 that exposes a portion of the drain electrode 62. The pixel electrode 68 is formed on the passivation layer 64 and is connected to the drain electrode 62 via the drain contact hole 66.
FIGS. 3A to 3E are schematic cross-sectional views showing an array substrate including an inverted staggered TFT in accordance with a manufacturing process thereof of the related art.
In FIG. 3A, a gate electrode 52 is formed by depositing and patterning a conductive material such as aluminum (Al), Al alloy, copper, tungsten (W), or molybdenum (Mo) on a substrate 50.
Next, a gate insulating layer 54 is formed by depositing an inorganic insulating material, such as silicon nitride or silicon oxide, on the substrate 50 where the gate electrode 52 is formed.
In FIG. 3B, amorphous silicon and doped amorphous silicon are deposited on the gate insulating layer 54 and patterned into an active layer 56 and an ohmic contact layer 58, respectively. For example, the amorphous silicon is deposited by a plasma enhanced chemical vapor deposition (PECVD) after decomposing a silane gas (SiH4) by radio frequency (RF) power. Forming the doped amorphous silicon includes preparing a chamber (not shown) where the substrate 50 having the amorphous silicon formed thereon is disposed and injecting a doping gas such as silane (SiH4), a dilution gas of hydrogen, phosphine (PH3) and diborane (B2H6), into the chamber. Here, when the gas pressure reaches a predetermined level, impurities such as phosphorous (P) or boron (B) may be incorporated as dopants into the amorphous silicon by providing RF power in the chamber.
The active layer 56 and the ohmic contact layer 58 can be formed having predetermined patterns by performing a mask process for patterning the amorphous silicon layer and the doped amorphous silicon layer.
FIG. 3C, source and drain electrodes 60 and 62 are formed by depositing and patterning a conductive material, such as the same material as the gate electrode material, on the ohmic contact layer 58. Here, the source and drain electrodes 60 and 62 are spaced apart from each other by an opening portion 59 that exposes a portion of the ohmic contact layer 58.
Sequentially, a portion of the ohmic contact layer 58 corresponding to the opening portion 59 is removed and a portion of the active layer 56 corresponding to the opening portion 59 is exposed. The exposed portion of the active layer 56 is defined as a channel region (not shown).
The active layer 56 and the ohmic contact layer 58 form a semiconductor layer 57.
Using the above-described process, a TFT T including the gate electrode 52, the semiconductor layer 57, and source and drain electrodes 60 and 62 may be formed.
In FIG. 3D, a passivation layer 64 is formed by depositing an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiOx) or by coating an organic insulating layer such as benzocyclobutene (BCB) and acrylic resin on the substrate 50 where the source and drain electrodes 60 and 62 are formed.
Next, a drain contact hole 66 is formed by patterning the passivation layer 64. The drain contact hole 66 exposes a portion of the drain electrode 62.
In FIG. 3E, a pixel electrode 68 is formed by depositing and patterning a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), on the passivation layer 64. Here, the pixel electrode 68 is connected to the drain electrode 62 via the drain contact hole 66.
Although the semiconductor layer 57 of the inverted staggered TFT T includes amorphous silicon, the amorphous silicon is unsuitable for a large size LCD. It is because the amorphous silicon has a low mobility regarding an electron and a hole thereof.
As one means to solve the problem, a top gate TFT using polysilicon having a higher mobility than the amorphous silicon has been suggested.
FIG. 4 is a schematic cross-sectional view of a top gate type TFT according to the related art.
In FIG. 4, a top gate type TFT T includes an active layer 72 of polysilicon on a substrate 70, an ohmic contact layer 74 on the active layer 72 which has an opening portion 73 that exposes a central portion of the active layer 72, and source and drain electrodes 76 and 78 spaced apart from each other by the opening portion 73.
The opening portion 73 defines a channel region (not shown). A gate insulating layer 80 is formed on an entire surface of the substrate 70 where the active layer 72, the ohmic contact layer 74 and the opening portion 73 are formed. A gate electrode 82 is formed on the gate insulating layer 80 at a position corresponding to the opening portion 73. A passivation layer 84 is formed on the gate electrode 82 and has a drain contact hole 85 that exposes a portion of the drain electrode 78. A pixel electrode 86 is formed on the passivation layer 84 and is connected to the drain electrode 78 via the drain contact hole 85. For example, the active layer 72 is made of polysilicon formed by crystallizing amorphous silicon.
As explained above, the inverted staggered type or the top gate type TFT is manufactured through a complicated process for forming the active layer 72 and the ohmic contact layer 74. Furthermore, forming the array substrate includes forming the TFT T, and, for example, forming the TFT T is not independent from forming and the data line (not shown) applying signals to the source and drain electrodes 76 and 78 of the TFT T.
Therefore manufacturing the array substrate increases the process time and the production cost.
A TFT using a silicon nanowire has been suggested in order to solve this problem.
FIG. 5 is a schematic cross sectional view showing a structure of a TFT including a silicon nanowire according to the related art.
In FIG. 5, a gate electrode 92 is formed on a substrate 90, source and drain electrodes 98 and 99 are formed on both sides of the gate electrode 92, and a silicon nanowire 95 is disposed on the gate electrode 92 so as to directly contact the source and drain electrodes 98 and 99 through both sides thereof. Typically, forming the silicon nanowire 95 is performed before forming the source and drain electrodes 98 and 99.
To connect the silicon nanowire 95 and the source and drain electrodes 98 and 99, an insulating layer 96, such as an oxide layer of the silicon nanowire 95 surrounding a crystalline silicon 94 of the silicon nanowire 95, is removed at each end of the silicon nanowire 95 before forming the source and drain electrodes 98 and 99.
Accordingly, an additional process for connecting the silicon nanowire 95 and the source and drain electrodes 98 and 99 is required. Therefore, since the silicon nanowire 95 is unstably disposed on the gate electrode 92, an electric contact state between the semiconductor material, such as the silicon nanowire 95, and the metal layer, such as the source and drain electrodes 98 and 99, is unstable. Therefore, a number of variables may undesirably affect the operation of the device.